The design of integrated circuit chips continues to evolve from the original concept of having more than one function on a chip to a complete system of components on a chip. Fabrication technology continues to rapidly decrease the design features size and increase the manufacturability size of a chip. This enables a large number of functions, available to a designer, to be incorporated on a chip. Designers then, have the ability to create systems on an IC that are increasingly more complex, very large and require a high-level design language in order to build, verify and test integrated circuit systems.
The task of designing these integrated circuits is also very complex and time consuming, involving synthesizing, analyzing and optimizing many circuit parameters. Because of this complexity, electronic design automation (EDA) systems have been developed to assist designers in developing integrated circuit designs at multitude levels of abstraction.
To ease the design of a complex integrated circuit, design tasks may be divided up into multiple functional blocks with a plurality of levels of hierarchy. However, dividing up an integrated circuit design into multiple blocks and hierarchical levels can complicate the evaluation of the overall circuit design. Moreover an integrated circuit design may be so large in size or scale (e.g., 1 million gates or more), each partition may have numerous signal paths (e.g., hundreds of thousands of signal paths for data, address, control, and clock signals) and numerous input, output, or input/output ports (e.g., thousands of ports).
With giga-gate (e.g., 1 billion gates or more) scale integrated circuit designs, robust hierarchical solutions to analyzing integrated circuit designs become even more important. Limits of computer capacity have bound chip designers to implement giga gate chip designs hierarchically. However, dividing the semiconductor chip hierarchically and implementing it through software is a complex and involved process. The added prototyping complexity involved can be justified if the implementation process yields quick turnaround times without extra iterations or repetition in the design flow process. With a giga gate chip design, hierarchical design becomes the preferred choice, but fast turnaround times in chip closure remains a factor to reckon with.
Designing an integrated chip utilizing a hierarchical approach provides the designer a method to reduce turnaround time. Another method to further decrease turnaround time that is commonly deployed is to create partitions within the design. Especially when designs are very large in size and complexity, they may be partitioned into smaller blocks or partitions based upon logical hierarchy. Timing budgeting derives input and output delay constraints along with path exceptions for the timing closure of these hierarchical blocks or partitions, enabling the timing closure of all the blocks simultaneously. This helps designers by saving time and minimizes the computing infrastructure required.
Partitioning a design is beneficial for analyzing integrated circuits such as with time budgeting, however, designers may want to create a nested partition to further control the implementation parameters of a function or sub circuit within a partition. Existing budgeting methodologies typically allow for only one level of partition such that there is no straightforward design flow for handling time budgeting of nested partitions.
Timing budgets for data paths are usually automatically generated in early design stages when the integrated circuit design may be incomplete or have errors so that generated timing budgets may require manual correction and analysis. The process of automatic timing budgeting is usually focused on worst case scenarios i.e., overly pessimistic that may lead to errors. The timing budgeting for blocks or partitions are specifically an issue due to multiple paths that must be analyzed that may share a common input and output.
As the complexity of designing integrated circuits continues to push the limits of the design software infrastructure, the high level description languages may need to change in order to minimize the limitations/burden to the designer. The embodiment of this invention expands the capability of the design tools for the designers of integrated circuits such that timing goals of an integrated circuit design may be met.